1. Field of the Invention
This invention relates to a method for fabricating semiconductor devices and more particularly to a method suitable for fabricating complementary bipolar transistor.
2. Description of the Related Art
Recently, attention is centered to complementary bipolar transistors having both an npn transistor and a pnp transistor in combination and usable as devices enabling realization of LSIS operative at a very high speed with a low power consumption.
FIGS. 1A to 1E show a conventional method for fabricating a complementary bipolar transistor.
In the conventional process for fabricating a complementary bipolar transistor, as shown in FIG. 1A, after an n.sup.+ -type buried layer 2 and a p.sup.+ -type buried layer 3 are first formed in a p-type Si substrate 1, an n-type Si epitaxial layer 4 is stacked on the p-type Si substrate 1. A p-type impurity is next ion-implanted into a selective portion of the n-type Si epitaxial layer 4 corresponding to the site for a pnp transistor to make a p-well 5. Then, an n-type impurity is ion-implanted into a selective portion of the n-type Si epitaxial layer 4 corresponding to the site for an npn transistor to make an n.sup.+ -type layer 6, and a p-type impurity is selectively ion-implanted into the p-well 5 in the site for the pnp transistor to make a p.sup.+ -type layer 7.
After that, as shown in FIG. 1B, a field insulation film 8 comprising a SiO.sub.2 film is selectively stacked on the surface of the n-type Si epitaxial layer 4 for isolation of devices, and a device-isolating p.sup.+ -type layer 9 is formed in a portion of the n-type Si epitaxial layer 4 just under the field insulation film 8. The entire structure is next covered by an insulation film 10 such as SiO.sub.2 film, and selective portions of the insulation film 10 corresponding to the sites for the npn transistor and the pnp transistor are removed by etching to form holes 10a and 10b.
After a polycrystalline Si film is made on the entire surface, a p-type impurity is introduced into a selective portion of the polycrystalline Si film including the site for the base electrode of the npn transistor, and an n-type impurity is introduced into a selective portion of the polycrystalline Si film including the site for the base electrode of the pnp transistor, by ion implantation, for example. The polycrystalline Si film is then processed by etching to form a p.sup.+ -type polycrystalline Si film 11 of a shape corresponding to the base electrode of the npn transistor and an n.sup.+ -type polycrystalline Si film 12 of a shape corresponding to the base electrode of the pnp transistor as shown in FIG. 1C. After that, an insulation film 13 such as SiO.sub.2. film, is formed on the entire surface.
As shown in FIG. 1D, the insulation film 13 and the p.sup.+ -type polycrystalline Si film 11 are selectively removed by sequential etching to form a hole 14 at the site for the base and emitter layers of the npn transistor, and the insulation film 13 and the n.sup.+ -type polycrystalline Si film 12 are selectively removed by sequential etching to form a hole 15 at the site for the base and emitter layers of the pnp transistor. The p.sup.+ -type polycrystalline Si film 11 remaining after the hole 14 is made behaves as the base electrode 16, and the n.sup.+ -type polycrystalline Si film 12 remaining after the hole 15 is made behaves as the base electrode 17. After that, a thin insulation film (not shown) is formed to cover at least the n-type Si epitaxial layer 4 exposed through the hole 14 and the p-well 5 exposed through the hole 15. Via this insulation film, a p-type impurity is ion-implanted into the n-type Si epitaxial layer 4 through the hole 14 to form a p-type base layer 18, and an n-type impurity is ion-implanted into the 5 through the hole 15 to form an n-type base layer 19. Subsequently, after an insulation film is formed on the entire surface, it is etched back vertically of the substrate surface by anisotropic dry etching. As a result, side wall spacers 20 in the form of insulation films are made on side walls of the holes 14 and 15. The side wall spacers 20 behave to separate the base electrode 16 from the emitter electrode 21 referred to later and to separate the base electrode 17 from the emitter electrode 22 referred to later.
After another polycrystalline Si film is formed on the entire surface, an n-type impurity is introduced into a selective portion of the polycrystalline Si film including the site for the emitter electrode of the npn transistor, and a p-type impurity is introduced into a selective portion of the polycrystalline Si film including the site for the emitter electrode of the pnp transistor, by ion implantation, for example. The polycrystalline Si film is then processed by etching to form an n.sup.+ -type polycrystalline Si film behaving as the emitter electrode 21 of the npn transistor, and a p.sup.+ -type polycrystalline Si film behaving as the emitter electrode 22 of the pnp transistor.
After that, the structure is annealed. As a result, as shown in FIG. 1E, the n-type impurity in the emitter electrode 21 comprising the n.sup.+ -type polycrystalline Si film diffuses into the p-type base region 18 to form an n.sup.+ -type emitter layer 23 and the p-type impurity in the base electrode 16 comprising the p.sup.+ -type polycrystalline Si film diffuses into the n-type Si epitaxial layer 4 to form a p.sup.+ -type base-contact layer 24 coupled to the p-type base layer 18. Similarly, the p-type impurity in the emitter electrode 22 comprising the p.sup.+ -type polycrystalline Si film diffuses into the n-type base layer 19 to form a p.sup.+ -type emitter layer 25, and the n-type impurity in the base electrode 17 comprising the n.sup.+ -type polycrystalline Si film diffuses into the p-well 5 to form an n.sup.+ -type base-contact layer 26 coupled to the n-type base layer 19.
In this case, the n.sup.+ -type emitter layer 23, p-type base layer 18, p.sup.+ -type base-contact layer 24, n-type Si epitaxial layer 4 behaving as the collector layer, base electrode 16, emitter electrode 21, and so forth, make up the npn transistor having a double-layered polycrystalline Si structure, whereas the p.sup.+ -type emitter layer 25, n-type base layer 19, n.sup.+ -type base-contact layer 26, p-well 5 behaving as the collector layer, base electrode 17, emitter electrode 22, and so forth, make up the pnp transistor having a double-layered polycrystalline Si structure.
After that, although not shown, through some steps of forming an inter-layer insulation film, making a contact hole in the inter-layer insulation film, making wiring of aluminum (Al), etc., an intended complementary bipolar transistor is completed.
It is desirable that the npn transistor and the pnp transistor match in characteristics with each other because the performance of a complementary bipolar transistor is determined by either its npn transistor or pnp transistor that is inferior in characteristics. In this respect, the conventional complementary bipolar transistor referred to above is advantageous because its npn transistor and pnp transistor have approximately symmetrical shapes.
However, since the conventional method for manufacturing the complementary bipolar transistor described above makes the emitter layer of the npn transistor and the emitter layer of the pnp transistor by the process comprising: making the polycrystalline Si film; ion-implanting an impurity into the polycrystalline Si film; and making the ion-implanted impurity to diffuse from the polycrystalline Si film used as the source of the impurity, it does not match well with the in-situ phosphorus doped poly Si emitter technique used in a process for fabricating high-performance npn transistors, which comprises doping phosphorus as an n-type impurity upon making a polycrystalline Si film by CVD and forming an emitter layer by using the p-doped n.sup.+ -type polycrystalline Si film as the source of the impurity. Therefore, the conventional method has its limit in increasing the impurity concentration Q.sub.e of the emitter layer, decreasing the emitter resistance R.sub.e, and decreasing the annealing temperature, which disturbs improvements in performance of complementary bipolar transistors and compatibility of the method with a process for manufacturing sub-half-micron bipolar CMOSs.